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SMT Manufacturability Design Guidelines

2023-02-09 17:51:23

SMT Manufacturability Design Guidelines

  1. Design Strategy

All PCBs will be designed with the following preference guidelines for choice of components, placement, and track size. This strategy is intended to make maximum use of ANS Design and Manufacturing capabilities and to minimize overall manufacturing costs:

  1. Full SMT. Component side only
  2. Full SMT. on both Component and solder sides
  3. Mixed SMT. and pth. on component side only
  4. mixed smt. and pth. with active smds on the component side and passive components on solder side
  1. Physical Routing Guidelines

2.1 Signal Tracks

8-mil tracks with 8-mil minimum clearance will be used where higher density requirements dictate. Where required because of density requirements, it will be possible to use 6-mil tracks with 6-mil minimum clearance. This will be avoided if at all possible, and will not be done without approval by Physical Design Management. Base copper foil for boards routed with 8-mil or 6-mil tracks will be ½ ounce, typically, and will generally be plated up to 1 ounce finished weight. There will continue to be a requirement to use the largest track and clearance possible for a given PBA, starting from 0.025 inches/0.025 inches and working downward.

2.2 Power Tracks

Power supply and ground distribution busses (when not solid or hatched planes) may have to shrink on dense PBAs from the present standard of 0.025 inches minimum. The heavier track will be used if space permits. Where 0.025 inches track is used for the main distribution paths a smaller track (0.015 inches to 0.025 inches) must be used to connect to SMT component pads.

2.3 Minimum Component Spacings

  1. See Figures 4A, and 4B for component-to-component spacings for primary side layouts.
  2. See Figure 5 for component-to-component spacings for secondary side components that will be wave soldered.
  3. See Figure 6 for SMT component clearance to automatic insertion tooling.
  4. When components are placed on the secondary side of the PCB only low profile components should be used. If the components exceed a height of 0.215 inches test design engineering must be informed.
  5. Outer layer circuit traces must be spaced at least 0.125 inches from the cards edge.

3.1 Conductor Spacings

Rules governing acceptable layout practices for SMT devices are shown in Figures 7A and 7B. Unacceptable practices are shown in Figures 8A and 8B. Maximum conductor width as it enters a land area for an SMT part is 0.025 inches with a maximum of two 0.025 inches tracks entering any given land (on opposite ends).

The minimum allowed distance between an SMT solder pad and a tented via is 0.010 inches. If the via is not tented the minimum distance is 0.020 inches.

On the secondary side of the PCB the minimum allowed distance between exposed conductors is 0.030 inches. (Conductors are defined as traces, vias, test pads, and solder pads.)

3.2 PCB Construction

  1. Minimize the number of layers.
  2. Symmetrical construction of SMT boards is required to minimize the potential for bow and twist on either the bare or assemble boards. This is especially important for multi-layer PBAs. Four characteristics contribute to the symmetry of a board:
  1. The board must have an even number of conductive layers ex. 2, 4, 6, etc.
  2. Each layer of a conductive layer pair must be located equi-distant from the natural axis (center of the 0.062 inches typical board thickness dimension) and there must be approximately equal amounts of copper on each layer. Also, the majority of the circuit traces on each layer of a pair must be orthogonal to the other layer.
  3. All dielectric layers located equi-distant from the neutral axis must have the same thickness.
  4. Layout components to maintain uniform hole density over the entire surface of the board to minimize warp.

Standard panel size will be used to minimize setup times for manufacturing processes. The standard panel size may contain one or more PCBs depending on the card size. The individual PCBs will be sheared from the panel after al assembly processes. Figure 9 shows the standard panel dimensions.

Breakaway Option – Since PCBs will be assembled in a panel of multiples the individual cards must be removed from the panel. The typical way to remove individual card is by shearing them from the panel. Where applicable breakaways should be used to reduce the material handling requirements during assembly. Figures 10A and 10B shows two breakaway options to choose from.

Photo imagable solder mask is required with a maximum thickness of 0.003 inches.

For a low tech, low density card, standard epoxy mask is acceptable.

Tolerance of tooling hole diameters is –0.000 +0.002 inches.

Solder mask over bare copper must be used.

Minimum solder plating (or leveled) thickness over copper is 0.0003 inches with a maximum of 0.001 inches.

No solder mask allowed within 0.040 inches of a fiducial mark.

No solder mask is allowed on SMT pads.

Silkscreen Requirements

  1. No silkscreen material allowed on SMT pads or thru-hole pads.
  2. All polarized devices must have a polarity indicator silkscreened outside the components footprint.
  3. Silkscreen reference locators outside the components footprint. (If space is a constraint, large-polarized components must have priority.)
  4. Silkscreen reference locators and all other marking such that they can be read from one board orientation. (Two orientations maximum)

3.3 Card Edge Clearance

To meet UL requirements, absolute minimum card-edge design clearance for any conductor will be 0.060 inches. This must include any possible tolerance of routing or shearing the board from a panel. From an assembly aspect a minimum edge clearance of 0.150-.200 inches is required on the primary and secondary sides of the PCB.

Internal tracks and planes must not be designed closer than 0.050 inches to the card edge.

3.4 Placement of Polarized Components
It is preferred that all polarized components be placed on the PCB in the same orientation.

3.5 Wave Soldering Layout Guidelines
When discrete components (or active component) require attachment to the secondary side of the PCB utilizing the wave soldering process, special layout rules apply:

  1. Layout components with their termination oriented as shown in Figure 11.
  2. Layout components with acceptable component-to-component clearances as shown in Figure 5. Proper clearances will insure the components will solder proper during wave soldering.
  3. Avoid staggering components as shown in Figure 12A and 12B. Staggering causes a shadowing which results in openings and acceptable distances between components are shown in Figures 12A and 12B.
  4. Do not put bare traces (traces that are not covered wit solder mask) nearer than 0.030 inches to SMT pads on the secondary side. If this rule is violated shorting (bridging) during wave soldering is likely to occur.
  5. The maximum trace width leading to SMT pads can be 0.025 inches. This will eliminate heat sinking effects.
  6. Avoid placing components in heavily heat sinked areas. For example, under large components or connected to a ground plane.

3.6 Via Hole Considerations and Constraints

VIAs used in SMT and FINELINE designs will use 0.015 inch finished diameter holes in a pad with a minimum diameter of 0.032 inches. All vias will be “tented” (covered with solder mask) on both sides of PWB to minimize soldering problems and to insure a good vacuum seal on the incircuit tester.

VIAS that have been tented can be placed under components.

In situations where the VIAS are not tented with solder mask “DO NOT PLACE VIAS UNDER LOW PROFILE COMPONENTS.” Low profile components are defined as components wit bodies less than 0.012 inches above the cards surface. Most discrete resistors and capacitors fall into the low profile category.

Through VIAS are the preferred type but blind VIAS or buried VIAS can be used if required due to space constraints. Blind and buried VIAS should be avoided if possible!

Un-tented VIAS must be a minimum of 0.020 inches from SMT pads (see Figure 7B). If the VIAS are tented, the VIAS must be a minimum of 0.010 inches from respective SMT pads.

3.7 Tooling Hole Requirements
Tooling holes are required for auto assembly processes. The standard tooling hole diameter is 0.127+0.002/-0.000 inches diameter. PWBs will typically be assembled in standard panel form as shown in Figure 9.
All assembly tooling holes must be unplated.

  1. Unplated tooling holes shall be placed on each individual PCB in diagonal corners
  2. The standard tooling hole diameter is 0.127 inches (shall not be less than 0.090 inches in diameter).
  3. Traces must not be closer than 0.050 inches from the tooling holes on the primary and secondary sides of the PCB. Traces must not be closer than 0.025 inches from the tooling holes on inner layers. Components can be no closer than 0.125 inches from the tooling holes.

3.8 Fiducial Mark Requirements

Fiducial marks are required for automatic placement of surface mounted devices (SMDs). The fiducial marks allow the placement equipment to optically recognize the artwork pattern on the PCB. The fiducial marks dimensional requirements are shown in Figure 13.

The fiducial marks should be located in three corners of individual PCBs as shown in Figure 14. Two fiducial marks should also be located around large SMT devices (larger than 68 pin) or fine pitch devices.

3.9 Design for Thermal Balance

If densely populated areas and nondensely populated areas exist on a single layout then thermal mismatch can be experienced during the reflow process. This means components on one area of the card may get too hot while the other areas have cold solder joints.

PLCCs normally cause thermal mismatch due to their size. The following rules apply:

  1. If PLCCs in 9 square inches on the boards result in more than 5 times the mass in any other 9 square inches on the board then, the PLCCs in that area should be a minimum of 0.350 inches apart.
  2. Distribute the surface area of ground planes as uniformly as possible.
  3. Avoid large voids in power and ground planes to minimize warp and signal noise.
  4. Power and ground planes should be on symmetrical layers to minimize warp. They must also be equal distance from the center.
  5. A SMT pad must not be part of ground plane. SMT pads must be a minimum of 0.030 inches from a mass of ground plane.

3.10 Dead Space

Dead space is required for manufacturing since the conveyors are used to transport the boards by its edges during manufacturing processes and for fitting test fixtures. Figure 15 shows dead space requirements.

Alternatives to dead space on individual PCBs are the use of panels or breakouts. Breakaways can be used to handle the board through manufacturing and can be removed after test.

3.11 Components Under Components
Placement of low profile components under other components on the same side of the PCB should be avoided. Components under components are very difficult to inspect, troubleshoot or repair.

3.12 Standard Hole Sizes
Use the minimum number of hole sizes as possible (8 or less).

3.13 Trace Run Paths
Take the shortest practicle distance between two points. Keep traces as far away from exposed conductors as possible. If solder mask is poorly registered or the mask is damaged shorting could occur if circuits are too dense. See Figure 3.

  1. Testability Guideline of SMT layouts

The following guidelines are presented to summarize testability layout rules for PCBs that will utilize an in-circuit test.

  1. Test Pads
  1. A 0.032 inch solid square test pad should be used.
  2. Provide a minimum of one test pad for each specified electrical node, if not accessible at a plated through hole pin.
  3. Test pads should be laid out 0.100 inch centers (0.050 inch is acceptable as a last resort and must be approved by the Test Design Engineering).
  4. Assure all test points are to be laid out on the solder side unless otherwise specified by test design engineering.
  5. No more than 40 test pads are allowed per square inch.
  6. All test pads must be coated with solder to allow good electrical contact during probing. DO NOT APPLY SOLDER MASK ON TEST PADS.
  7. For each voltage and ground, provide at least one test pad for each ½ amp of current (worst case) required to power-up the PCB. A minimum of two test pads for each voltage and ground is required. (Information supplied by Test Design Engineering.)
  8. Test pads should be indicated on final, PPR and DEM schematics.
  9. Test pads will be represented as intelligent parts in the PBA Design and Schematic Capture Tools.
  1. Others
  1. Use pull up or pull down resistors on input lines.
  2. Connect unused gates and control lines to VCC or ground through a resistor.
  3. Interrupt jumpers to isolate sensitive test areas and oscillators.
  4. Probe contact on unused control lines and gate output.
  5. Probe contact on both sides at unused inverters.
  1. All PWBs using SMT components will require the following markings. Text height shall be a minimum of 0.050 inches.
  1. The company name (minimum 0.100 inches)
  2. Part number (minimum 0.080 inches)
  3. Revision number (minimum 0.080 inches)
  4. Reference designators (minimum .050 inches)
  5. The board drilling number etches in copper on the solder side of the PCB.

If the PBA requires markings to be used by the customer (option blocks, switches, LEDs, etc.) these markings must be screened or etched on the board. A minimum of 0.060 inch text.

A minimum of 0.020 inches designed clearance is required between SMT pads and silkscreened markings.

Ink used must not deteriorate or bleed contaminants on to SMT or thru-hole pads under exposure to IR Reflow, Vapor phase Reflow, Freon cleaning or wave soldering.


PBA Requirements – Electronic Format
Gerber Files – 274X Format
Drill or Fabrication Drawing
X-Y Drill Plan
Primary Side Assembly Drawing
Secondary Side Assembly Drawing
Silkscreen Drawing
Bill of Materials
SMT Primary Side
SMT Secondary Side
Board Drilling
Board Blank
Drill Plan
Specifications and Layer Configuration Data
Supplemental Mechanical Detail Drawing
Paste Screen
Primary Side Detail
Secondary Side Detail (If required)
Test, Performance, and Technical Specs
Mechanical Details (Front Panels, Covers, etc.)
Process Specs

Manufacturing Data
Test Drill Files
X-Y Coordinates of all Components
Electronic BOM (Excel, CSV, or TXT)
Conventional Component Auto-insertion
Auto Inspection Data
Test Node Data


SMT device shape dimensions will be based on IPC-SM-782. The pad geometries defined must be incorporated into the CAD shape libraries.

When the geometries are updated to improve manufacturability, the CAD date base must be updated. When old designs are updated, the updated pad geometries should be incorporated. ENs and ECOs must specify which pad geometries should change.


If any new information becomes available or if new requirements arise based on experience the following procedure should be followed to insure the information is documented in the official SMT design guidelines.

  1. Submit the attached “DESIGN GUIDELINES REVISION REQUEST FORM” to the AME manager. Along with the revision request form attach a summary of the proposed change or addition.
  2. The AME group will review the request and call a Design guideline review meeting. The proposed change will be discussed and if approved the proper sign offs will be obtained (see Revision Request Form).
  3. The Design Guidelines will be updated during the first week of each quarter. Revisions will be issued as temporary guidelines until incorporated into the official guidelines.
  4. The attached “Revision Log” must be filled out to reflect each revision.

Figure 4A

Primary Side Layout

Figure 4B

Primary Side Layout

Figure 5

Secondary Side Layout

Note: All dimensions in mils/.001 inches (shown from pad to pad)

FIGURE 5 (continued)

Secondary Side Layout


Note: All dimensions in mils/.001 inches (shown from pad to pad)

Figure 6

Clinch Tooling to SMT Clearance (Bottom side)

Figure 7A

Acceptable Layout

Figure 7B

Acceptable Layout

Figure 8A

Unacceptable Layout

Figure 8B

Unacceptable Layout

Figure 9

Figure 10A

Figure 10B

Figure 11

Secondary Side Layout

Figure 12A

Avoid staggering wave soldered adjacent chip components

Figure 12B

Secondary Side Layout

** Avoid staggering or placement of uncommon package types behind each other for wave soldering.

** For mix technology designs, the use of sots, tantalum capacitors, and SOIC’s should be avoided on the secondary side.

Figure 13

Fiducial Pad

Figure 14

Figure 15